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hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com features switch mode controller for single switch drivers ? buck ? boost ? buck-boost ? sepic works with high side current sensing closed loop control of output current high pwm dimming ratio internal 250v linear regulator (can be extended using external zener diodes) internal 2% voltage reference (0c < t a < 85c) constant frequency or constant off-time operation programmable slope compensation enable & pwm dimming +0.2a/-0.4a gate drive output short circuit protection output over voltage protection synchronization capability programmable mosfet current limit applications rgb backlight applicationsbattery powered led lamps other dc/dc led drivers ?? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? general description the hv9911 is a current mode control led driver ic designed to control single switch pwm converters (buck, boost, buck- boost, or sepic), in a constant frequency or constant off-time mode. the controller uses a peak current control scheme, (with programmable slope compensation), and includes an internal transconductance ampli?er to control the output current in closed loop, enabling high output current accuracy. in the constant frequency mode, multiple hv9911s can be synchronized to each other, or to an external clock, using the sync pin. programmable mosfet current limit enables current limiting during input under voltage and output overload conditions. the ic also includes a 0.2a source and 0.4a sink gate driver for high power applications. an internal 9.0 - 250v linear regulator powers the ic, eliminating the need for a separate power supply for the ic. hv9911 provides a ttl compatible, pwm dimming input that can accept an external control signal with a duty ratio of 0-100% and a frequency of up to a few kilohertz. the ic also provides a fault output which, can be used to disconnect the leds in case of a fault condition, using an external disconnect fet. the hv9911 based led driver is ideal for rgb backlight applications with dc inputs. the hv9911 based led lamp drivers can achieve ef?ciency in excess of 90% for buck and boost applications. typical application circuit - boost switch-mode led driver ic with high current accuracy 6 7 10 9 15 8 13 14 16 11 12 5 3 1 24 c in c dd c ref r r2 r r1 r l1 r l2 r t r slope r sc sc r cs r ovp1 r ovp2 c o d1 q1 l1 q2 c c r s vin vdd gnd sc rt ref clim iref sync pwmd comp fdbk fault ovp cs gate hv9911 downloaded from: http:///
2 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com typical application circuit - buck typical application circuit - sepic l1 6 7 10 9 15 8 13 16 14 5 3 11 12 1 24 cc c in c dd c ref r r2 r r1 r l1 r l2 r t r slope r sc r cs c o d1 q1 r s hv7800 vin vdd gnd sc rt ref clim iref sync pwmd comp fdbk fault gate cs ovp hv9911 6 7 10 9 15 8 13 14 16 11 12 5 3 1 24 c in c dd c ref r r2 r r1 r l1 r l2 r t r slope r sc r cs r ovp1 r ovp2 c o d1 q1 l1 q2 c c r s l2 c1 vin vdd gnd sc rt ref clim iref sync pwmd comp fdbk fault ovp cs gate hv9911 downloaded from: http:///
3 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com ordering information device package options 16-lead soic hv9911 HV9911NG-G -g indicates package is rohs compliant (green)absolute maximum ratings parameter value v in to gnd -0.5v to +250v v dd to gnd -0.3v to +13.5v cs1, cs2 to gnd -0.3v to (v dd + 0.3v) pwmd to gnd -0.3v to (v dd + 0.3v) gate to gnd -0.3v to (v dd + 0.3v) all other pins to gnd -0.3v to (v dd + 0.3v) continuous power dissipation (t a = +25c) (derate 10.0mw/c above +25c) 1000mw junction to ambient thermal impedance 82 o c/w operating ambient temperature range -40c to +85c junction temperature +125c storage temperature range -65c to +150c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the speci?cations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin con?guration vin vdd fdbk fault comp pwmd iref ref gnd clim cs gate ovp sc sync rt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 product marking 16-lead soic (ng) (top view) 16-lead soic (ng) sym parameter min typ max units conditions input v indc input dc supply voltage range * - (1) - 250 v dc input voltage i insd shut-down mode supply current * - - 1.0 1.5 ma pwmd connected to gnd, v in = 24v internal regulator v dd internally regulated voltage * - 7.25 7.75 8.25 v v in = 9.0 - 250v, i dd(ext) = 0, pwmd connected to gnd uvlo v dd undervoltage lockout threshold - - 6.65 6.90 7.20 v v dd rising ?uvlo v dd undervoltage lockout hysteresis - - - 500 - mv --- v dd(ext) steady state external voltage that can be applied at the v dd pin ( 2) - - - - 12 v --- electrical characteristics(the speci?cations are at t a = 25c and v in = 24v, unless otherwise noted.) y = last digit of year sealed ww = week sealed l = lot number c = country of origin a = assembler id* = green packaging *may be part of top marking top marking bottom marking hv9911ng yww llllllll ccccccccc aaa notes: * denotes the speci?cations which apply over the full operating ambient temperature range of -40c < t a < +85c. 1. see application section for minimum input voltage. 2. parameters are not guaranteed to be within speci?cations if the external v dd voltage is greater than v dd(ext) or if v dd < 7.25v. package may or may not include the following marks: si or downloaded from: http:///
4 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com sym parameter min typ max units conditions reference v ref ref pin voltage (0c < t a < 25c) - - 1.225 1.25 1.275 v ref bypassed with a 0.1f capacitor to gnd; i ref = 0; v dd = 7.75v; pwmd = gnd ref pin voltage (-40c < t a < 85c) - - 1.225 1.25 1.275 v refline line regulation of reference voltage - - 0 - 20 mv ref bypassed with a 0.1f capacitor to gnd; i ref = 0; v dd = 7.25 - 12v; pwmd = gnd v refload load regulation of reference voltage - - 0 - 10 mv ref bypassed with a 0.1f capacitor to gnd; i ref = 0-500; pwmd = gnd pwm dimming v pwmd(lo) pwmd input low voltage * - - - 0.80 v v dd = 7.25v - 12v v pwmd(hi) pwmd input high voltage * - 2.0 - - v v dd = 7.25v - 12v r pwmd pwmd pull-down resistance - - 50 100 150 k? v pwmd = 5.0v gate i source gate short circuit current - - 0.2 - - a v gate = 0v; v dd = 7.75v i sink gate sinking current - - 0.4 - - a v gate = 7.75v ; v dd = 7.75v t rise gate output rise time - - - 50 85 ns c gate = 1nf; v dd = 7.75v t fall gate output fall time - - - 25 45 ns c gate = 1nf; v dd = 7.75v over voltage protection v ovp ic shut down voltage * - 1.215 1.25 1.285 v v dd = 7.25 - 12v ; ovp rising current sense t blank leading edge blanking - - 100 - 375 ns --- t delay1 delay to output of comp comparator - - - - 180 ns comp = v dd ; c lim = ref; v cs = 0 to 600mv step t delay2 delay to output of c limit comparator - - - - 180 ns comp = v dd ; c lim = 300mv; v cs = 0 to 400mv step v offset comparator offset voltage - - -10 - 10 mv --- internal transconductance opamp gb gain bandwidth product - # - 1.0 - mhz 75pf capacitance at comp pin a v open loop dc gain - - 66 - - db output open v cm input common-mode range - # -0.3 - 3.0 v --- v o output voltage range - # 0.7 - 6.75 - v dd = 7.75v g m transconductance - - 340 435 530 a/v --- v offset input offset voltage - - -2.0 - 4.0 mv --- i bias input bias current - # - 0.5 1.0 na --- electrical characteristics (cont.) (the speci?cations are at t a = 25c and v in = 24v, unless otherwise noted.) notes: * denotes the speci?cations which apply over the full operating ambient temperature range of -40c < t a < +85c. # denotes guaranteed by design. downloaded from: http:///
5 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com oscillator f osc1 oscillator frequency * - 88 100 112 khz r t = 909k? f osc2 oscillator frequency * - 308 350 392 khz r t = 261k? d max maximum duty cycle - - - 90 - % --- i outsync sync output current - - - 10 20 a --- i insync sync input current - - 0 - 200 a v sync < 0.1v output short circuit t off propagation time for short circuit detection - - - - 250 ns i ref = 200mv; fdbk = 450mv; fault goes from high to low t rise,fault fault output rise time - - - - 300 ns 1.0nf capacitor at fault pin t fall,fault fault output fall time - - - - 200 ns 1.0nf capacitor at fault pin g fault ampli?er gain at iref pin - - 1.8 2 2.2 i ref = 200mv slope compensation i slope current sourced out of sc pin - - 0 - 100 a --- g slope internal current mirror ratio - - 1.8 2 2.2 - i slope = 50a; rc sense = 1.0k? sym parameter min typ max units conditions functional block diagram v bg vin vdd ref gate + _ + _ 13r r fdbk iref comp gnd pwmd por rt sync s r q g m + _ clim 100ns blanking + _ 2 cs dis sc + _ ramp 1:2 dis + _ v bg ovp r s q fault por dis q one shot linear regulator electrical characteristics (cont.) (the speci?cations are at t a = 25c and v in = 24v, unless otherwise noted.) notes: * denotes the speci?cations which apply over the full operating ambient temperature range of -40c < t a < +85c. downloaded from: http:///
6 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com functional description the built in linear regulator of the hv9911 can operate up to 250v at the vin pin. the linear regulator provides an internally regulated voltage of 7.75v (typ) at vdd if the input voltage is in the range of 9.0 C 250v. this voltage is used to power the ic and also provide the power to external circuits connected at the vdd and vref pins. this linear regulator can be turned off by overdriving the vdd pin using an external boostrap circuit at voltages higher than 8.25v (up to 12v). in practice, the input voltage range of the ic is limited by the current drawn by the ic. thus, it becomes important to determine the current drawn by the ic to ?nd out the maximum and minimum operating voltages at the vin pin. the main component of the current drawn by the ic is the current drawn by the switching fet driver at the gate pin. to estimate this current, we need to know a few parameters of the fet being used in the design and the switching frequency. the typical waveform of the current being sourced out of gate is shown in fig. 1. fig. 2 shows the equivalent circuit of the gate driver and the external fet. the values of v dd and r gate for the hv9911 are 7.75v and 40 respectively. note: the equations given below are approximations and are to be used only for estimation purposes. the actual values will differ somewhat from the computed values . consider the case when the external fet is fds3692 and the switching frequency is f s = 200khz with an led string voltage v o = 80v. from the datasheet of the fet, the following parameters can be determined: c iss = 746pf c gd = c rss = 27pf c gs = c iss - c gd = 719pf v th = 3.0v power topology i pk i 1 i avg t 1 t 2 t 3 0 fig. 1. current sourced out of gate at fet turn-on driver fig. 2. equivalent circuit of the gate driver hv9911 c gd c gs v dd r gate downloaded from: http:///
7 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com parameter formula value (for given example) i pk v dd / r gate 193.75ma i 1 (v dd - v th ) / r gate 118.75ma t 1 -r gate ? c iss ? in (i 1 / i pk ) 14.61ns t 2 [(v o - v th ) ? c gd ] / i 1 [(v in - v th ) ? c gd ] / i 1 (for a boost converter) (for a buck converter) 17.5ns t 3 2.3 ? r gate ? c gs 66ns i avg [i 1 ? (t 1 + t 2 ) + 0.5 ? (i pk - i 1 ) ? t 1 + 0.5 ? i 1 ? t 3 ] ? f s 1.66ma the total current being drawn from the linear regulator for a typical hv9911 circuit can be computed as follows (the values provided are based on the continuous conduction mode boost design in the application note - an-h55). current formula typical value quiescent current 1000a 1000a current sourced out of ref pin (v ref / r l1 + r l2 ) + (v ref / r r1 + r r2 ) 100a current sourced out of rt pin 6 v / r t 13.25a current sourced out of sc pin (1 / 2) ? (2.5v / r slope ) 30.8a current sourced out of cs pin 2.5v / r slope 61.6a current drawn by fet gate driver i avg 1660a total current drawn from the linear regulator 2.865ma note: for a discontinuous mode converter, the currents sourced out of the sc and cs pin will be zero. when the external fet is being turned on, current is being sourced out of the gate and that current is being drawn from the input. thus, the average current drawn from v dd (and thus from v in ) needs to be computed. without going into the details of the fet operation, the various values in the graph of fig. 1 can be computed as follows: downloaded from: http:///
8 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com maximum input voltage at vin pin computed using the power dissipation limit the maximum input voltage that the hv9911 can withstand without damage if the regulator is drawing about 2.8ma will depend on the ambient temperature. if we consider an ambi- ent temperature of 40c, the power dissipation in the pack- age cannot exceed: p max = 1000mw - 10mw ? (40 o c - 25 o c) = 850mw the above equation is based on package power dissipation limits as given in the absolute maximum limits section of this datasheet. to dissipate a maximum power of 850mw in the package, the maximum input voltage cannot exceed: v inmax = p max / i total = 296v since the maximum voltage is far greater than the actual input voltage (24v), power dissipation will not be a problem for this design. for this design, at 24v input, the increase in the junction temperature of the ic (over the ambient) will be ? = v in ? i total ? ja = 5.64 o c where ja is the junction to ambient thermal impedance of the 16-lead soic package of the hv9911. minimum input voltage at vin pin the minimum input voltage at which the converter will start and stop depends on the minimum voltage drop required for the linear regulator. the internal linear regulator will regu- late the voltage at the vdd pin when v in is between 9.0 and 250v. however, when v in is less than 9.0v, the converter will still function as long as v dd is greater than the under voltage lockout. thus, the converter might be able to start at input voltages lower than 9.0v. the start/stop voltages at the vin pin can be determined using the minimum voltage drop across the linear regulator as a function of the current drawn. this data is shown in fig. 3 for different junction tem- peratures. fig. 3. graph of the input current vs mini- mum voltage drop across linear regulator for different junction temperatures assume a maximum junction temperature of 85c (this give a reasonable temperature rise of 45c at an ambient tempera- ture of 40c). at 2.86ma input current, the minimum voltage drop from fig. 3 can be approximately estimated to be v drop = 0.75v. however, before the ic starts switching the current drawn will be the total current minus the gate drive current. in this case, that current is i q_total = 1.2ma. at this current level, the voltage drop is approximately v drop1 = 0.4v. thus, the start/stop v in voltages can be computed to be: vin start = uvlo max + v drop1 = 7.2v + 0.4v = 7.60v vin stop = uvlo max - 0.5v + v drop = 7.2v - 0.5v + 0.75v = 7.45v note: in some cases, if the gate drive draws too much current, vin start might be less than vin stop . in such cases, the control ic will oscillate between on and off if the input voltage is between the start and stop voltages. in these circumstances, it is recommended that the input voltage be kept higher than vin stop . minimum drop in linear regulator (v) input current (ma) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -40 c 25 c 85 c 125 c downloaded from: http:///
9 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com reference hv9911 includes a 2% accurate, 1.25v reference, which can be used as the reference for the output current as well as to set the switch current limit. this reference is also used internally to set the over voltage protection threshold. the reference is buffered so that it can deliver a maximum of 500a external current to drive the external circuitry. the reference should be bypassed with at least a 10nf low esr capacitor. note: in order to avoid abnormal startup conditions, the bypass capacitor at the ref pin should not exceed 0.22f. oscillator the oscillator can be set in two ways. connecting the oscillator resistor between the rt and gate pins will program the off-time. connecting the resistor between rt and gnd will program the time period. in both cases, resistor r t sets the current, which charges an internal oscillator capacitor. the capacitor voltage ramps up linearly and when the voltage increases beyond the internal set voltage, a comparator triggers the set input of the internal sr ?ip-?op. this starts the next switching cycle. the time period of the oscillator can be computed as: t s r t ? 11pf slope compensation for converters operating in the constant frequency mode, slope compensation becomes necessary to ensure stability of the peak current mode controller, if the operating duty cycle is greater than 0.5. choosing a slope compensation which is one half of the down slope of the inductor current ensures that the converter will be stable for all duty cycles. slope compensation can be programmed by two resistors r slope and r sc . assuming a down slope of ds (a/s) for the inductor current, the slope compensation resistors can be computed as: r slope = (10 ? r sc ) / (ds ? 10 6 ? t s ? r cs ) a typical value for r sc is 499?. note: the maximum current that can be sourced out of the sc pin is 100a. this limits the minimum value of the r slope resistor to 25k?. if the equation for slope compensation produces a value of r slope less than this value, then r sc would have to be increased accordingly. it is recommended that r slope be chosen in the range of 25 - 50k?. current sense the current sense input of the hv9911 includes a built in 100ns (minimum) blanking time to prevent spurious turn off due to the initial current spike when the fet turns on. the hv9911 includes two high-speed comparators - one is used during normal operation and the other is used to limit the maximum input current during input under voltage or overload conditions. the ic includes an internal resistor divider network, which steps down the voltage at the comp pin by a factor of 15. this stepped-down voltage is given to one of the comparators as the current reference. the reference to the other comparator, which acts to limit the maximum inductor current, is given externally. it is recommended that the sense resistor r cs be chosen so as to provide about 250mv current sense signal. current limit current limit has to be set by a resistor divider from the 1.25v reference available on the ic. assuming a maximum operating inductor current i pk (including the ripple current), the voltage at the clim pin can be set as: v clim 1.2 ? i pk ? r cs + ( 5 ? r sc / r slope ) ? 0.9 note that this equation assumes a current limit at 120% of the maximum input current. also, if v clim is greater than 450mv, the saturation of the internal opamp will determine the limit on the input current rather than the clim pin. in such a case, the sense resistor r cs should be reduced till v clim reduces below 450mv. it is recommended that no capacitor be connected between clim and gnd. fault protection the hv9911 has built-in output over-voltage protection and output short circuit protection. both protection features are latched, which means that the power to the ic must be recycled to reset the ic. the ic also includes a fault pin which goes low during any fault condition. at startup, a monoshot circuit, (triggered by the por circuit), resets an internal ?ip-?op which causes fault to go high, and remains high during normal operation. this also allows the gate drive to function normally. this pin can be used to drive an external disconnect switch (q2 in the typical boost application circuit on pg.1), which will disconnect the load during a fault condition. this disconnect switch is very important in a boost converter, as turning off the switching downloaded from: http:///
10 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com fet (q 1 ) during an output short circuit condition will not remove the fault (q 1 is not in the path of the fault current). the disconnect switch will help to disconnect the shorted load from the input. over voltage protection over voltage protection is achieved by connecting the output voltage to the ovp pin through a resistive divider. the voltage at the ovp pin is constantly compared to the internal 1.25v. when the voltage at this pin exceeds 1.25v, the ic is turned off and fault goes low. output short circuit protection the output short circuit condition is indicated by fault. at startup, a monoshot circuit, (triggered by the por circuit), resets an internal ?ip-?op, which causes fault to go high, and remains high during normal operation. this also allows the gate drive to function normally. the steady state current is re?ected in the reference voltage connected to the transconductance ampli?er. the instantaneous output current is sensed from the fdbk terminal of the ampli?er. the short circuit threshold current is internally set to 200% of the steady state current. during short circuit condition, when the current exceeds the internally set threshold, the sr ?ip-?op is set and fault goes low. at the same time, the gate driver of the power fet is inhibited, providing a latching protection. the system can be reset by cycling the input voltage to the ic. note: the short circuit fet should be connected before the current sense resistor as reversing r s and q 2 will affect the accuracy of the output current (due to the additional voltage drop across q 2 which will be sensed). synchronization the sync pin is an input/output (i/o) port to a fault tolerant peer-to-peer and/or master clock synchronization circuit. for synchronization, the sync pins of multiple hv9911 based converters can be connected together, and may also be connected to the open drain output of a master clock. when connected in this manner, the oscillators will lock to the device with the highest operating frequency. when synchronizing multiple ics, it is recommended that the same timing resistor, corresponding to the switching frequency, be used in all the hv9911 circuits. on rare occasions, given the length of the connecting lines for the sync pins, a resistor between sync and gnd may be required to damp any ringing due to parasitic capacitances. it is recommended that the resistor chosen be greater than 300k?. when synchronized in this manner, a permanent high or low condition on the sync pin will result in a loss of synchronization, but the hv9911 based converters will continue to operate at their individually set operating frequency. since loss of synchronization will not result in total system failure, the sync pin is considered fault tolerant. note: the hv9911 is designed to sync up to four ics at a time without the use of an external buffer. to sync more than four ics, it is recommended that a buffered external clock be used. internal 1mhz transconductance ampli?er hv9911 includes a built in 1mhz transconductance ampli?er, with tri-state output, which can be used to close the feedback loop. the output current sense signal is connected to the fdbk pin and the current reference is connected to the iref pin. the output of the opamp is controlled by the signal applied to the pwmd pin. when pwmd is high, the output of the opamp is connected to the comp pin. when pwmd is low, the output is left open. this enables the integrating capacitor to hold the charge when the pwmd signal has turned off the gate drive. when the ic is enabled, the voltage on the integrating capacitor will force the converter into steady state almost instantaneously. the output of the opamp is buffered and connected to the current sense comparator using a 15:1 divider. the buffer helps to prevent the integrator capacitor from discharging during the pwm dimming state. linear dimming linear dimming can be accomplished by varying the voltage at the iref pin, as the output current is proportional to the voltage at the iref pin. this can be done either by using a potentiometer from the ref pin or by applying an external voltage source at the iref pin. note: due to the offset voltage of the transconductance opamp, pulling the iref pin very close to gnd will cause the internal short circuit comparator to trigger and shut down the ic. this limits the linear dimming range of the ic. however, a 1:10 linear dimming range can be easily obtained. it is recommended that the pwmd pin be used to get zero output current rather than pull the i ref pin to gnd. downloaded from: http:///
11 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com pwm dimming pwm dimming can be achieved by driving the pwmd pin with a ttl compatible source. the pwm signal is connected internally to the three different nodes C the transconductance ampli?er, the fault output, and the gate output. when the pwmd signal is high, the gate and fault pins are enabled, and the output of the transconductance opamp is connected to the external compensation network. thus, the internal ampli?er controls the output current. when the pwmd signal goes low, the output of the transconductance ampli?er is disconnected from the compensation network. thus, the integrating capacitor maintains the voltage across it. the gate is disabled, so the converter stops switching and the fault pin goes low, turning off the disconnect switch. the output capacitor of the converter determines the pwm dimming response of the converter, since it has to get charged and discharged whenever the pwmd signal goes high or low. in the case of a buck converter, since the inductor current is continuous, a very small capacitor is used across the leds. this minimizes the effect of the capacitor on the pwm dimming response of the converter. however, in the case of a boost converter, the output current is discontinuous, and a very large output capacitor is required to reduce the ripple in the led current. thus, this capacitor will have a signi?cant impact on the pwm dimming response. by turning off the disconnect switch when pwmd goes low, the output capacitor is prevented from being discharged, and thus the pwm dimming response of the boost converter improves dramatically. note: disconnecting the capacitor might cause a sudden spike in the capacitor voltage as the energy in the inductor is dumped into the capacitor. this might trigger the ovp comparator if the ovp point is set too close to the maximum operating voltage. thus, either the capacitor has to sized slightly larger or the ovp set point has to be increased. note: the hv9911 ic might latch-up if the pwmd pin is pulled 0.3v below gnd, causing failure of the part. this abnor- mal condition can happen if there is a long cable between the pwm signal and the pwmd pin of the ic. it is recom- mended that a 1.0k resistor be connected between the pwmd pin and the pwm signal input to the hv9911. this resistor, when placed close to the ic, will damp out any ringing that might cause the voltage at the pwmd pin to go below gnd. avoiding false shutdowns of the hv9911 the hv9911 has two fault modes which trigger a latched protection mode, an over current (or short circuit) protection, and an over voltage protection. to prevent false triggering due to the tripping of the over voltage comparator, (due to noise in the gnd traces on the pcb), it is recommended that a 1.0 - 10nf capacitor be connected between the ovp pin and gnd. although this capacitor will slow down the response of the over voltage protection circuitry somewhat, it will not affect the overall performance of the converter, as the large output capacitance in the boost design will limit the rate of rise of the output voltage. in some cases, the over current protection may be triggered during pwm dimming, when the fault goes high and the disconnect switch is turned on. this triggering of the over current protection is related to the parasitic capacitance of the led string (shown as a lumped capacitance c led in fig. 4). during normal pwm dimming operation, the hv9911 maintains the voltage across the output capacitor (c o ), by turning off the disconnect switch and preserving the charge in the output capacitance when the pwm dimming signal is low. at the same time, the voltage at the drain of the disconnect fet is some non-zero value v d . when the pwm dimming signal goes high, fet q 2 is turned on. this causes the voltage at the drain of the fet (v d ) to instantly go to zero. assuming a constant output voltage v o , i sense = c led ? d(v o - v d ) / dt = -c led ? dv d / dt in this case, the rate of fall of the drain voltage of the disconnect fet is a large value (since the fet turns on very quickly) and this causes a spike of current through the sense resistor, which could trigger the over current protection (depending on the parasitic capacitance of the led string). to prevent this condition, a simple rc low pass ?lter network can be added as shown in fig. 5. typical values are r f = 1.0k and c f = 470pf. this ?lter will block the fdbk pin from seeing the turn-on spike and normalize the pwm dimming operation of the hv9911 boost converter. this will have minimal effect on the stability of the loop but will increase the response time to an output short. if the increase in the response time is large, it might damage the output current sense resistor due to exceeding its peak-current rating. downloaded from: http:///
12 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com the increase in the short circuit response time can be computed using the various component values of the boost converter. consider a boost converter with a nominal output current i o = 350ma, an output sense resistor r s = 1.24, led string voltage v o = 100v and an output capacitor c o = 2.0mf. the disconnect fet is a tn2510n8 from supertex which has a saturation current i sat = 3a (at v gs = 6.0v). the increase in the short circuit response time due to the rc ?lter can then be computed as: this increase is found to be negligible (note that the equation is valid for t << r s ? c o . in this case, r s ? c o = 2.48s, and the condition holds. sizing the output sense resistor to avoid exceeding the peak-current rating of the output sense resistor during short circuit conditions, the power rating of the resistor has to be chosen properly. in this case, the maximum power dissipated in the sense resistor is: p sc = i 2 sat ? r s = 11w from the datasheet for a 1.24, 1/4w resistor, the maximum power it can dissipate for a single 1ms pulse of current is 11w. since the total short circuit time is about 350ns (including the 300ns time for turn off), the resistor should be able to handle the current. ?t r f ? c f ? in i sat - i o =1k? ? 470pf ? in 1- 1 - 0.35a 66ns i o 3a - 0.35a r ovp2 c o r s q2 fault fdbk c led v o v d i sense r ovp2 c o r s q2 fault fdbk c led v o v d i sense c f fig. 4. output of the boost converter show- ing led parsed capacitance fig. 5. adding a low-pass filter to prevent pulse triggering downloaded from: http:///
13 hv9911 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com pin # pin description 1 vin this pin is the input of a 250v high voltage regulator. 2 vdd this is a power supply pin for all internal circuits. it must be bypassed with a low esr capacitor t o gnd (at least 0.1uf). 3 gate this pin is the output gate driver for an external n-channel power mosfet. 4 gnd ground return for all circuits. this pin must be connected to the return path from the input. 5 cs this pin is used to sense the drain current of the external power fet. it includes a built-in 100ns (min) blanking time. 6 sc slope compensation for current sense. a resistor between sc and gnd will program the slope compensation. in case of constant off-time mode of operation, slope compensation is unnecessary and the pin can be left open. 7 rt this pin sets the frequency or the off-time of the power circuit. a resistor between rt and gnd will program the circuit in constant frequency mode. a resistor between rt and gate will program the circuit in a constant off-time mode. 8 sync this i/o pin may be connected to the sync pin of other hv9911 circuits and will cause the oscillator s to lock to the highest frequency oscillator. 9 clim this pin provides a programmable input current limit for the converter. the current limit can be set by using a resistor divider from the ref pin. 10 ref this pin provides 2% accurate reference voltage. it must be bypassed with at least a 10nf - 0.22f capacitor to gnd. 11 fault this pin is pulled to ground when there is an output short circuit condition or output over voltage condition. this pin can be used to drive an external mosfet in the case of boost converters to disconnect the load from the source. 12 ovp this pin provides the over voltage protection for the converter. when the voltage at this pin exceed s 1.25v, the gate output of the hv9911 is turned off and fault goes low. the ic will turn on when the power is recycled. 13 pwmd when this pin is pulled to gnd (or left open), switching of the hv9911 is disabled. when an external ttl high level is applied to it, switching will resume. 14 comp stable closed loop control can be accomplished by connecting a compensation network between comp and gnd. 15 iref the voltage at this pin sets the output current level. the current reference can be set using a resi stor divider from the ref pin. 16 fdbk this pin provides output current feedback to the hv9911 by using a current sense resistor. pin description downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receive s an adequate product liability indemnification insuran ce agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for p ossible omissions and inaccuracies. circuitry and s pecifications are subject to change without notice. for the lates t product specifications refer to the supertex inc. website: http//www.supertex.com. ?2009 all rights reserved. unauthorized use or reproduct ion is prohibited. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com 14 hv9911 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the la test package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv9911 a092309 16-lead soic (narrow body) package outline (ng) 9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 9.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation ac, issue e, sept. 2005. * this dimension is not speci?ed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-16song, version g041309. d seating plane gauge plane l l1 l2 top view side view view a-a view b view b 1 e1 e a a2 a1 a a seating plane e b h h 16 1 note 1 note 1 (index area d/2 x e1/2) note: this chamfer feature is optional. if it is not present, then a pin 1 identi?er must be located in th e index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1. downloaded from: http:///

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